28C datasheet, 28C pdf, 28C data sheet, datasheet, data sheet, pdf, Atmel, K 32K x 8 Paged CMOS E2PROM. 28C Microchip. K (32K x 8) CMOS Electrically Erasable PROM. PIN CONFIGURATION. Top View. A 1 A7. A A *NC. Vcc. WE. . A2. 5 WE. A dimensions section on page 14 of this data sheet. ORDERING INFORMATION. PLCC−32 . 28C− 28C− Units. Min. Max. Min. Max. tRC.
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The page write operation of the AT28C allows datasheey to bytes of data to be written into the device during a single internal programming period. The outputs are put in the high impedance state when either CE or OE is high. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 addi- tional bytes.
28C256 – 28C256 256K 250ns Parallel EEPROM Datasheet
CE to Output Delay. During a write cycle, the addresses and 1 to bytes of data are internally latched, freeing the address and data bus for other opera- tions. If precautions are not taken, inad- vertent writes may occur during transitions of the host sys- tem power supply. Automatic Page Write Operation. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses refer to Software Data Protection Algorithm.
An optional software data protection mechanism is available to guard against inad- vertent writes. Refer to AC Programming Waveforms.
Input Test Waveforms and Measurement Level. All bytes dur- ing a page write operation must reside on the same page as defined by the state of the A6 – A14 inputs. The address is latched on the falling edge of CE or WE, whichever occurs last.
Manufac- tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to ns with power dissipation of just mW.
When enabled, the software data protection SDPwill prevent inadvertent writes. Reading the toggle bit may begin at any time during the write cycle.
Fast Write Dwtasheet Times.
28C256 Datasheet PDF
After setting SDP, any attempt to write to the device with- out the 3-byte command sequence will start the internal write timers. For each WE high to low transition during the page write operation, A6 datsaheet A14 must be the same.
Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin.
Hardware features 28c265 against inadvertent writes to the AT28C in the follow- ing ways: Exposure 28c2256 absolute maximum rating conditions for extended periods may affect device reliability.
This dual- line control gives designers flexibility in preventing bus contention in their system. Hardware and Software Data Protection. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. Each successive byte must be written within Fast Read Access Time – ns. Its K of memory is organized as 32, words by 8 bits. X can be V. OE to Output Delay.
A software controlled data protection feature has been implemented on the AT28C By raising A9 to 12V. After writing the 3-byte command sequence and after t. Page Write Cycle Time: Once the end of a write cycle has been detected a new access for a read or write can begin.
28C – 28C K ns Parallel EEPROM Technical Data
The data in the enable and disable command se- quences is not written to the device and the memory ad- dresses used in the sequence may be written with data 28c56 either a byte or page write operation. Address to Output Delay.
2c256 CE and OE are low datsheet WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. Atmel’s 28C has additional features to ensure high quality and manufacturability.
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification 28cc256 not implied.
It should be noted, that once protected the host may still perform a byte or page write to the AT28C PROM memory are available to the user for device. Search field Part name Part description. This is done by pre- ceding the data to be written by the same 3-byte command sequence used to enable SDP.
CE may be delayed up to t. All Output Voltages with Respect to Ground All command se- quences must conform to the page write timing specifica- tions.